Integrated circuits with high voltage and high density capacitors and methods of producing the same

ABSTRACT

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a high voltage capacitor having a first high voltage plate, a second high voltage plate directly overlying the first high voltage plate, and a high voltage dielectric film between the first and second high voltage plates. The integrated circuit also includes a high density capacitor with a first high density plate that is about co-planar with the second high voltage plate, a second high density plate directly overlying the first high density plate, and a thin high density dielectric film positioned between the first and second high density plates.

TECHNICAL FIELD

The technical field generally relates to integrated circuits with highvoltage and high density capacitors and methods of producing the same,and more particularly relates to integrated circuits with high voltageand high density capacitors as well as precision metal resistors andmethods of producing the same.

BACKGROUND

Capacitors are one type of electronic component used in many integratedcircuits. Capacitors include two conductive plates separated by adielectric layer. A charge can be temporarily stored on one of theconductive plates, and that charge can then be used for a wide varietyof purposes. The dielectric layer can be polarized to store energy, sothe dielectric layer increases the capacitor's charge capacity. Whenstoring energy, there is an electric field across the dielectric layer,a positive charge on one of the conductive plates, and a negative chargeon the other conductive plate.

Different capacitor designs have different properties, such as theamount of charge stored and the potential difference between theconductive plates. The capacitance of a capacitor is the ratio of theamount of electric charge (denoted by the symbol Q) on the conductiveplates to the potential difference (measured in volts) between theconductive plates. Sometimes it is desirable for a capacitor to becapable of maintaining a large potential difference between theconductive plates (e.g., for a high voltage capacitor), and in othercircumstances it is desirable for a capacitor to store a large amount ofelectric charge (e.g., for a high density capacitor). A thickerdielectric layer tends to have a smaller permittivity, and smallerpermittivities are more conducive to high voltage capacitors than tohigh density capacitors. Therefore, the manufacturing steps are somewhatdifferent for producing a high voltage capacitor and a high densitycapacitor, and the incorporation of different manufacturing steps tendsto drive up the cost of production. As such, integrated circuitsgenerally include either high voltage or high density capacitors, butnot both.

Accordingly, it is desirable to provide integrated circuits that includeboth high voltage and high density capacitors, and methods for producingthe same. In addition, it is desirable to provide integrated circuitsthat with additional electronic components formed with the capacitors,which tends to reduce the cost of such integrated circuits, and methodsof producing the same. Furthermore, other desirable features andcharacteristics of the present embodiment will become apparent from thesubsequent detailed description and the appended claims, taken inconjunction with the accompanying drawings and this background of theinvention.

BRIEF SUMMARY

Integrated circuits and methods of producing the same are provided. Inan exemplary embodiment, an integrated circuit includes a high voltagecapacitor having a first high voltage plate, a second high voltage platedirectly overlying the first high voltage plate, and a high voltagedielectric film between the first and second high voltage plates. Theintegrated circuit also includes a high density capacitor with a firsthigh density plate that is about co-planar with the second high voltageplate, a second high density plate directly overlying the first highdensity plate, and a thin high density dielectric film positionedbetween the first and second high density plates.

An integrated circuit is provided in another embodiment. The integratedcircuit includes a high voltage capacitor overlying a substrate, wherethe high voltage capacitor includes a first high voltage plate and asecond high voltage plate directly overlying the first high voltageplate. A high voltage dielectric film is positioned between the firstand second high voltage plates, where the high voltage dielectric filmhas a high voltage dielectric film thickness. A high density capacitoralso overlies the substrate. The high density capacitor includes a firsthigh density plate, a second high density plate directly overlying thefirst high density plate, and a thin high density dielectric filmbetween the first and second high density plates. The thin high densitydielectric film has a thin high density dielectric film thickness thatis less than the high voltage dielectric film thickness.

A method of producing an integrated circuit is provided in yet anotherembodiment. The method includes forming a first high voltage plate in afirst interlayer dielectric, and forming a thick dielectric layeroverlying the first high voltage plate and the first interlayerdielectric. A first electrode layer is formed overlying the thickdielectric layer, and a thin dielectric layer is formed overlying thefirst electrode layer. The thin dielectric layer has a thickness that isless than a thickness of the thick dielectric layer. A second electrodelayer is formed overlying the thin dielectric layer. A high densitycapacitor is formed, where the high density capacitor includes a portionof the first electrode layer, a portion of the second electrode layer,and a portion of the thin dielectric layer. A high voltage capacitor isalso formed, where the high voltage capacitor includes the first highvoltage plate, a portion of the thick dielectric layer, and a portion ofthe first electrode layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments will hereinafter be described in conjunctionwith the following drawing figures, wherein like numerals denote likeelements, and wherein:

FIGS. 1-7 are cross-sectional views illustrating portions of anintegrated circuit and methods for its fabrication in accordance withexemplary embodiments.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the various embodiments or the application anduses thereof. Furthermore, there is no intention to be bound by anytheory presented in the preceding background or the following detaileddescription. Embodiments of the present disclosure are generallydirected to integrated circuits and methods for fabricating the same.The various tasks and process steps described herein may be incorporatedinto a more comprehensive procedure or process having additional stepsor functionality not described in detail herein. In particular, varioussteps in the manufacture of integrated circuits are well-known and so,in the interest of brevity, many conventional steps will only bementioned briefly herein or will be omitted entirely without providingthe well-known process details.

Reference is made to an exemplary embodiment illustrated in FIG. 1. Anintegrated circuit 10 includes a substrate 12 comprising semiconductormaterial. As used herein, the term “semiconductor material” will be usedto encompass semiconductor materials conventionally used in thesemiconductor industry from which to make electrical devices.Semiconductor materials include monocrystalline silicon materials, suchas the relatively pure or lightly impurity-doped monocrystalline siliconmaterials typically used in the semiconductor industry, as well aspolycrystalline silicon materials, and silicon admixed with otherelements such as germanium, carbon, and the like. In addition,“semiconductor material” encompasses other materials such as relativelypure and impurity-doped germanium, gallium arsenide, zinc oxide, glass,and the like. In many embodiments, the substrate 12 primarily includes amonocrystalline silicon semiconductor material. The substrate 12 may bea bulk silicon wafer (as illustrated) or may be a thin layer of siliconon an insulating layer (commonly known as silicon-on-insulator or SOI,not illustrated) that, in turn, is supported by a carrier wafer. One ormore electronic components (not illustrated) may be formed in or on thesubstrate 12 as is typical for many integrated circuits 10.

A first interlayer dielectric 14 overlies the substrate 12, where thefirst interlayer dielectric is an electrically insulating material. Asused herein, an “electrically insulating material” is a material with aresistivity of about 1×10⁴ ohm meters or more, and an “electricallyconductive material” is a material with a resistivity of about 1×10⁴ ohmmeters or less. As used herein, the term “overlying” means “over” suchthat an intervening layer may lie between the first interlayerdielectric 14 and the substrate 12, and “on” such that the firstinterlayer dielectric 14 physically contacts the substrate 12. Moreover,the term “directly overlying” means a vertical line passing through theupper component also passes through the lower component, such that atleast a portion of the upper component is directly over at least aportion of the lower component. It is understood that the integratedcircuit 10 may be moved such that the relative “up” and “down” positionschange, so reference to a “vertical” line means a line that is aboutperpendicular to the surface of the substrate 12. In an exemplaryembodiment, the first interlayer dielectric 14 includes silicon dioxide,which may be formed by chemical vapor deposition using silane andoxygen, but many other electrically insulating materials or methods offormation may be used in alternate embodiments.

A first ILD gap 16 may be formed in an upper surface of the firstinterlayer dielectric 14, where the first ILD gap 16 extends into thefirst interlayer dielectric 14 for some distance but does not penetrateor pass completely through the first interlayer dielectric 14. In oneexemplary embodiment, a first ILD hard mask 18 is formed overlying thefirst interlayer dielectric 14, such as by reacting ammonia anddichlorosilane in a low pressure chemical vapor deposition furnace toform silicon nitride for the first ILD hard mask 18. A layer ofphotoresist (not shown) is used for patterning the first ILD hard mask18 to form the first ILD gap 16. The photoresist may be deposited byspin coating and patterned by exposure to light or other electromagneticradiation through a mask with transparent sections and opaque sections.The light causes a chemical change in the photoresist such that eitherthe exposed portions or the non-exposed portions can be selectivelyremoved. The desired locations may be removed with an organic solvent,and the photoresist remains overlying the other areas of the first ILDhard mask 18. Exposed portions of the first ILD hard mask 18 can then beselectively removed, such as with a hot phosphoric acid etch, while thefirst ILD hard mask 18 underlying the remaining photoresist remains inplace. The patterned first ILD hard mask 18 exposes the portions of thefirst interlayer dielectric 14 where the first ILD gap 16 will be formedwhile protecting other areas of the first interlayer dielectric 14.Photoresist may be selectively removed with an oxygen containing plasmaafter the first ILD hard mask 18 is patterned.

The exposed areas of the first interlayer dielectric 14 are etched withan etchant that is selective to the material of the first interlayerdielectric 14 over the material of the first ILD hard mask 18. Forexample, a wet etch with dilute hydrofluoric acid is selective tosilicon dioxide (which may be in the first interlayer dielectric 14)over silicon nitride (which may be in the first ILD hard mask 18). In anexemplary embodiment, the depth of the first ILD gap 16 is determined bythe time the etch is allowed to proceed, but in alternate embodiments anetch stop layer (not illustrated) may be formed within the firstinterlayer dielectric 14 to better control the depth of the first ILDgap 16, and a dry etch technique such as a reactive ion etch may beused. Many other etchants or etching techniques may be used in alternateembodiments, as understood by those skilled in the art, so the exampledescribed herein is merely exemplary and is not intended to limit themeans of formation. Photoresists and hard masks may be used forpatterning and forming many components of the integrated circuit 10, andrepetitive discussions of this process are generally omitted to simplifyand clarify this description.

Referring to FIG. 2 with continuing reference to FIG. 1, the first ILDhard mask 18 is removed, such as with a wet etch using hot phosphoricacid. The first ILD gaps 16 may be filled with an electricallyconductive material to form a first high voltage plate 20 and anoptional third high density plate 22. The electrically conductivematerial formed in the first ILD gap 16 is metallic in some embodiments,and may include about 80 mass percent copper or more in someembodiments. However, other electrically conductive materials and/orother metals may be used in alternate embodiments. In an exemplaryembodiment, the first high voltage plate 20 and optional third highdensity plate 22 may be formed by depositing copper by electroless orelectrolytic plating from a solution such as a sulfuric acid copperbath, and subsequent chemical mechanical planarization to remove thecopper overburden. A copper seed layer (not illustrated) may be formedto improve adhesion between the first interlayer dielectric 14 and thefirst high voltage plate 20 and/or the third high density plate 22.

In some embodiments, the first high voltage plate 20 and the third highdensity plate 22 are formed at the same time using the same processtechniques. As such, the properties of the first high voltage plate 20and the third high density plate 22 may be substantially the same. Asused herein, the term “substantially the same” means about the same,where the subject matter is intended to be the same but may varyslightly due to process variability or process errors. For example, thefirst high voltage plate 20 and the third high density plate 22 may besubstantially co-planar, meaning a distance between bottom surfaces of(1) the first high voltage plate 20 and (2) the third high density plate22 and a top surface of the substrate 12 (illustrated in FIG. 1) arewithin about 10 percent or each other, or within about 5 percent of eachother, or within about 1 percent of each other in various embodiments.As used herein, the term “co-planar” refers to the components beingsubstantially co-planar on a plane that is substantially parallel to thetop surface of the substrate 12. In a similar manner, a composition ofthe first high voltage plate 20 is substantially the same as acomposition of the third high density plate 22. For example, the masspercent of each element in the first high voltage plate 20 is withinabout 10 percent, or about 5 percent, or about 1 percent of the masspercent of that element in the third high density plate 22 in variousembodiments. Also, a thickness 21 of the first high voltage plate 20 anda thickness 23 of the third high density plate 22 may be substantiallythe same, such as within about 10 percent, or 5 percent, or 1 percent ofeach other in various embodiments.

Reference is now made to an exemplary embodiment illustrated in FIG. 3.A thick dielectric layer 24 is formed overlying the first interlayerdielectric 14, the first high voltage plate 20, and the optional thirdhigh density plate 22. The thick dielectric layer 24 includes anelectrically insulating material, and may include silicon nitride insome embodiments. Silicon nitride can be formed by low pressure chemicalvapor deposition using ammonia and polydimethyl silane. The thickdielectric layer 24 may have a thickness (indicated by reference number26) of from about 500 angstroms to about 2,000 angstroms, or from about500 angstroms to about 3,000 angstroms, or from about 500 angstroms toabout 5,000 angstroms in various embodiments. The thickness 26 of thethick dielectric layer 24 may be set such that the thick dielectriclayer 24 has a pre-determined permittivity, so the thickness 26 of thethick dielectric layer 24 may vary somewhat based on the materialcomposition of the thick dielectric layer 24. The thick dielectric layer24 may serve as cap layer for the first interlayer dielectric 14 and anycomponents formed therein in some embodiments, where a cap layer canlimit atomic migration during subsequent annealing steps.

In an exemplary embodiment, a first electrode layer 28 is formedoverlying the thick dielectric layer 24, where the first electrode layer28 is formed of an electrically conductive material. In someembodiments, the first electrode layer 28 includes metals, such astitanium nitride, tantalum nitride, tantalum, or others. In someembodiments, the first electrode layer 28 includes about 50 mass percentor more of titanium, tantalum, or a combination thereof. A thindielectric layer 30 is formed overlying the first electrode layer 28,where the thin dielectric layer 30 is formed of an electricallyinsulating material. The thin dielectric layer 30 may include siliconnitride, which can be formed as described above, but the thin dielectriclayer 30 may include several other materials in alternate embodiments.For example, the thin dielectric layer 30 may include silicon dioxide,silicon-carbon-nitrogen-hydrogen compounds known by the name NBLoK, highK dielectric materials such as hafnium oxide, aluminum hafnium oxide,aluminum oxide, or other materials. The thin dielectric layer 30 has athickness indicated by the reference number 32 that is thinner than thethickness 26 of the thick dielectric layer 24. For example, thethickness 32 of the thin dielectric layer 30 may be from about 50angstroms to about 500 angstroms, or from about 100 angstroms to about500 angstroms, or from about 50 to about 400 angstroms in variousembodiments. As with the thick dielectric layer 24 described above, thethickness 32 of the thin dielectric layer 30 may be set to produce acertain permittivity, so the thickness 32 may vary depending on thematerial of the thin dielectric layer 30. In general, the permittivityof the thick dielectric layer 24 is less than the permittivity of thethin dielectric layer 30. A second electrode layer 34 is formedoverlying the thin dielectric layer 30, where the second electrode layer34 includes an electrically conductive material. As with the firstelectrode layer 28 described above, the second electrode layer 34 mayinclude a metal, and may include about 50 mass percent or more oftitanium, tantalum, or a combination thereof. An electrode layer hardmask and photoresist (not illustrated) are formed and patternedoverlying the second electrode layer 34, in the same manner as describedabove.

Referring to the exemplary embodiment illustrated in FIG. 4, withcontinuing reference to FIG. 3, the second electrode layer 34 and thethin dielectric layer 30 are removed except for at selected locations toform one or more second high density plates 36 and one or more thin highdensity dielectric films 38. The second high density plate 36 directlyoverlies and, in some embodiments, is disposed directly upon the thinhigh density dielectric film 38. In an embodiment with the secondelectrode layer 34 including titanium nitride, the second electrodelayer 34 may be removed in areas not covered by the electrode layer hardmask (not illustrated) with a reactive ion etch using chlorine andargon. In embodiments with the thin dielectric layer 30 includingsilicon nitride, the thin dielectric layer 30 may be removed where notcovered by the electrode layer hard mask (not illustrated) with areactive ion etch. In one optional embodiment, the second high densityplate 36 may directly overlie the third high density plate 22, but inother embodiments the second high density plate 36 directly overlies thefirst interlayer dielectric 14 and the substrate 12 (illustrated in FIG.1), but does not directly overlie a third high density plate 22. In someembodiments, there may be more than one second high density plate 36,and some of the second high density plates 36 may directly overlierespective third high density plates 22 and some of the second highdensity plates 36 may be positioned in areas that do not directlyoverlie a third high density plate 22.

Portions of the first electrode layer 28 are then selectively removed toform a second high voltage plate 40, a resistor plate 42, and a firsthigh density plate 44, as illustrated in FIG. 5 with continuingreference to FIG. 4. The portions of the first electrode layer 28 may beselectively removed using lithography and an optional hard mask (notillustrated), in the same manner as described above. In someembodiments, the second high voltage plate 40 directly overlies thefirst high voltage plate 20, and the portion of the thick dielectriclayer 24 that is positioned between the first and second high voltageplates 20, 40 serves as a high voltage dielectric film 50. The firsthigh voltage plate 20 may extend beyond the area covered by the secondhigh voltage plate 40 to facilitate an electrical connection to thefirst high voltage plate 20. The resistor plate 42 overlies the thickdielectric layer 24, and the first high density plate 44 directlyunderlies the second high density plate 36 and the thin high densitydielectric film 38. The first high density plate 44 may extend beyondthe area covered by the second high density plate 36 to facilitateseparate electrical connections, as mentioned above for the first andsecond high voltage plates 20, 40. In embodiments where the second highdensity plate 36 directly overlies the third high density plate 22, thefirst high density plate 44 also directly overlies the third highdensity plate 22. In such embodiments, the portion of the thickdielectric layer 24 positioned between the first and third high densityplates 44, 22 serves as a thick high density dielectric film 52. Thethick high density dielectric film 52 and the high voltage dielectricfilm 50 are formed from the thick dielectric layer 24 in someembodiments, so all three components have substantially the samethickness and composition, as described above for the first high voltageplate 20 and the third high density plate 22.

The second high voltage plate 40, the resistor plate 42, and the firsthigh density plate 44 are formed from the first electrode layer 28, sothe second high voltage plate 40, the resistor plate 42, and the firsthigh density plate 44 are all about co-planar and all have about thesame composition. For example, the composition of any element in one ofthe second high voltage plate 40, the resistor plate 42, or the firsthigh density plate 44 may be within about 10 mass percent, or withinabout 5 mass percent, or within about 1 mass percent of the compositionof that element in any other of the second high voltage plate 40, theresistor plate 42, and the first high density plate 44, in variousembodiments. The second high voltage plate 40, the resistor plate 42,and the first high density plate 44 are all about co-planar, so adistance between a top surface of the substrate 12 (illustrated inFIG. 1) and a bottom surface of the second high voltage plate 40, theresistor plate 42, or the first high density plate 44 is within about 10percent, or about 5 percent, or about 1 percent of the distance betweenthe top surface of the substrate 12 (illustrated in FIG. 1) and a bottomsurface of any other of the second high voltage plate 40, the resistorplate 42, and the first high density plate 44, in various embodiments.

The first and second high voltage plates 20, 40 are separated by thehigh voltage dielectric film 50, and this forms a high voltage capacitor54. The first and second high density plates 44, 36 are separated by thethin high density dielectric film 38, and this forms a high densitycapacitor 56. The permittivity of the thin high density dielectric film38 is greater than that of the high voltage dielectric film 50 in someembodiments, at least in part because the thin high density dielectricfilm 38 is thinner than the high voltage dielectric film 50, so the highvoltage capacitor 54 is capable of maintaining a larger potentialdifference (voltage) between the capacitor plates than the high densitycapacitor 56. Because of the difference in permittivity, the highdensity capacitor 56 is capable of storing a larger amount of chargethan the high voltage capacitor 54 for equivalent areas of therespective capacitor plates. The method of producing the high voltageand high density capacitors 54, 56 within the same integrated circuit10, as described herein, allows for greater circuit design flexibilitycompared to an integrated circuit with only one of the high voltage orhigh density capacitors 54, 56. Additionally, the use of one layer toproduce plates for two different types of capacitors may also reducemanufacturing costs compared to separate plate production for each typeof capacitor. The high density capacitor 56 that includes a third highdensity plate 22 further increases the circuit design flexibility,because such a high density capacitor 56 can store a larger amount ofcharge for a given area than a high density capacitor 56 without a thirdhigh density plate 22.

Referring to FIG. 6, an etch stop layer 58 may be formed overlying thesecond high voltage plate 40, the resistor plate 42, the second highdensity plate 36, the thick dielectric layer 24, and any othercomponents that are exposed. In an exemplary embodiment, the etch stoplayer 58 includes silicon nitride, NBLoK, silicon carbon nitride, orother electrically insulating materials. Silicon nitride may bedeposited by chemical vapor deposition using ammonia and dichlorosilane,for example, but other material may also be used in the etch stop layer58 in various embodiments. A second interlayer dielectric 60 thatincludes, for example, silicon dioxide may be formed overlying the etchstop layer 58 and the components underlying the etch stop layer 58. Anupper surface of the second interlayer dielectric 60 may be planarized,such as with chemical mechanical planarization, in some embodiments.

Contacts 62 may be formed through the second interlayer dielectric 60 toform an electrical connection with each of the capacitor plates (20, 22,36, 40, and 44), and with the resistor plate 42, as illustrated in FIG.7. Vias (not illustrated) may be formed through the second interlayerdielectric 60 using lithography and a reactive ion etch selective to thematerial of the second interlayer dielectric 60 over the material of theetch stop layer 58, followed by a selective removal of the etch stoplayer 58 in the vias (not illustrated.) In an example where the secondinterlayer dielectric 60 includes silicon dioxide and the etch stoplayer 58 includes silicon nitride, the second interlayer dielectric 60may be selectively removed with a reactive ion etch using hydrogenbromide and silicon tetrafluoride with oxygen, and the etch stop layer58 can be selectively removed with a hot phosphoric acid wet etch. Thecontacts 62 may then be formed within the vias (not illustrated). In anexemplary embodiment, the contacts 62 include an adhesion layer, abarrier layer, and a plug (not individually illustrated), which aresequentially deposited. For example, an adhesion layer of titanium maybe formed by low pressure chemical vapor deposition using titaniumpentachloride, a barrier layer of titanium nitride may be formed bychemical vapor deposition using titanium tetrabromide and ammonia, and aplug of tungsten may be formed by chemical vapor deposition usingtungsten hexafluoride and hydrogen. Other types of contacts are alsopossible, such as copper or other conductive materials.

At least two contacts 62 are in electrical communication with theresistor plate 42, where the two contacts 62 are a set distance apartalong the resistor plate 42, thus forming a resistor 64. The resistorplate 42 has a cross sectional area between the two contacts 62. Allmaterials have some resistance to the flow of electricity, and thatresistance is related to the cross sectional area perpendicular to theflow of electricity and the distance the electricity flows through thematerial. Therefore, the resistance of the resistor 64 can be controlledby establishing or selecting the material of the resistor plate 42, thecross-sectional area of the resistor plate 42 between the two contacts62, and the distance between the two contacts 62 through the resistorplate 42. Other factors may also influence the resistance of theresistor 64, such as the shape of the resistor plate 42, the amount ortype of silicide formed at the contact point between the resistor plate42 and the contacts 62, and other factors. The resistor plate 42 may bemetallic, so the resistance and temperature coefficient of resistance ofthe resistor plate 42 may be less than that of a resistor that has apolysilicon resistor plate. The term “metallic,” as used herein, means amaterial that includes at least about 50 mass percent of a metal ormore. As such, the resistor 64 may be a precision metal resistor 64 ascompared to a resistor formed with a polysilicon resistor plate. As usedherein, a “precision resistor” is a resistor primarily formed of amaterial with a lower resistance and temperature coefficient ofresistance than that of polysilicon. The economical process describedabove can be used to form (1) the resistor 64, (2) the high voltagecapacitor 54, and (3) the high density capacitor 56 that all overlie thesubstrate 12. A circuit designer has increased design flexibility for anintegrated circuit 10 when the two different types of capacitors areincluded in a single integrated circuit 10, and the addition of theresistor 64 further improves design flexibility.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiments are only examples, and are not intended to limitthe scope, applicability, or configuration of the application in anyway. Rather, the foregoing detailed description will provide thoseskilled in the art with a convenient road map for implementing one ormore embodiments, it being understood that various changes may be madein the function and arrangement of elements described in an exemplaryembodiment without departing from the scope, as set forth in theappended claims.

1. An integrated circuit comprising: a high voltage capacitor comprisinga first high voltage plate, a second high voltage plate directlyoverlying the first high voltage plate, and a high voltage dielectricfilm positioned between the first high voltage plate and the second highvoltage plate; a high density capacitor comprising a first high densityplate that is about co-planar with the second high voltage plate, asecond high density plate directly overlying the first high densityplate; and a thin high density dielectric film positioned between thefirst high density plate and the second high density plate; an etch stoplayer overlying the high voltage capacitor and the high densitycapacitor, wherein the etch stop layer comprises an electricallyinsulating material; and a second interlayer dielectric overlying theetch stop layer.
 2. The integrated circuit of claim 1 furthercomprising: a resistor comprising a resistor plate, wherein the resistorplate is about co-planar with the second high voltage plate and thefirst high density plate, wherein the etch stop layer overlies theresistor.
 3. The integrated circuit of claim 2 further comprising: athick dielectric layer underlying the resistor plate; and a firstinterlayer dielectric underlying the thick dielectric layer.
 4. Theintegrated circuit of claim 2 wherein: the resistor plate, the secondhigh voltage plate, and the first high density plate have about the samecomposition.
 5. The integrated circuit of claim 1 wherein a thickness ofthe high voltage dielectric film is greater than a thickness of the thinhigh density dielectric film.
 6. The integrated circuit of claim 1wherein the high density capacitor further comprises a third highdensity plate underlying the first high density plate.
 7. The integratedcircuit of claim 6 further comprising: a thick high density dielectricfilm positioned directly between the first high density plate and thethird high density plate, wherein a composition of the thick highdensity dielectric film is about the same as a composition of the highvoltage dielectric film.
 8. The integrated circuit of claim 7 wherein athickness of the thick high density dielectric film is about the same asa thickness of the high voltage dielectric film.
 9. The integratedcircuit of claim 6 wherein the first high voltage plate and the thirdhigh density plate have about the same composition.
 10. The integratedcircuit of claim 6 wherein the first high voltage plate and the thirdhigh density plate are about co-planar.
 11. The integrated circuit ofclaim 1 wherein: the second high voltage plate and the first highdensity plate have about the same composition.
 12. The integratedcircuit of claim 1 wherein the first high voltage plate comprises about80 mass percent copper or more, and the second high voltage platecomprises about 50 mass percent of a metal selected from the groupconsisting of titanium, tantalum, and a combination thereof.
 13. Theintegrated circuit of claim 1 wherein a permittivity of the high densitydielectric film is greater than a permittivity of the high voltagedielectric film.
 14. An integrated circuit comprising: a high voltagecapacitor overlying a substrate, wherein the high voltage capacitorcomprises a first high voltage plate, a second high voltage platedirectly overlying the first high voltage plate, and a high voltagedielectric film positioned between the first high voltage plate and thesecond high voltage plate, wherein the high voltage dielectric film hasa high voltage dielectric film thickness; a high density capacitoroverlying the substrate, wherein the high density capacitor comprises afirst high density plate, a second high density plate directly overlyingthe first high density plate, and a thin high density dielectric filmpositioned between the first high density plate and the second highdensity plate, wherein the thin high density dielectric film has a highdensity dielectric film thickness less than the high voltage dielectricfilm thickness; an etch stop layer overlying the high voltage capacitorand the high density capacitor, wherein the etch stop layer comprises anelectrically insulating material; and a second interlayer dielectricoverlying the etch stop layer.
 15. The integrated circuit of claim 14further comprising: a resistor overlying the substrate, wherein theresistor comprises a resistor plate.
 16. The integrated circuit of claim15 wherein the resistor plate, the second high voltage plate, and thefirst high density plate have about the same composition such that amass percent of each element in the resistor plate, the second highvoltage plate, and the first high density plate is within about 5percent of each other.
 17. The integrated circuit of claim 16 whereinthe resistor plate comprises about 50 mass percent or more of a metalselected from the group consisting of titanium, tantalum, and acombination thereof.
 18. The integrated circuit of claim 14 wherein: thehigh voltage dielectric film thickness if from about 500 angstroms toabout 2,000 angstroms; and the high density dielectric film thickness isfrom about 100 angstroms to about 500 angstroms.
 19. The integratedcircuit of claim 14 further comprising: a third high density platedirectly underlying the first high density plate; and a thick highdensity dielectric film positioned between the third high density plateand the first high density plate.
 20. A method of producing anintegrated circuit comprising: forming a first high voltage plate in afirst interlayer dielectric; forming a thick dielectric layer overlyingthe first high voltage plate and the first interlayer dielectric;forming a first electrode layer overlying the thick dielectric layer;forming a thin dielectric layer overlying the first electrode layer,wherein a thickness of the thin dielectric layer is less than athickness of the thick dielectric layer; forming a second electrodelayer overlying the thin dielectric layer; forming a high densitycapacitor, wherein the high density capacitor comprises a portion of thefirst electrode layer, a portion of the second electrode layer, and aportion of the thin dielectric layer; and forming a high voltagecapacitor, wherein the high voltage capacitor comprises the first highvoltage plate, a portion of the thick dielectric layer, and a portion ofthe first electrode layer.